Markus Grözing

Abstract

Ultra-high speed and bandwidth ADCs are necessary for communication systems that apply spectral efficient modulation formats to achieve date rates of 100Gbit/s and beyond. These ADCs must have a high absolute input bandwidth, a high sampling speed and good linearity. A key component of these ADCs is the analog front-end section between the analog signal input and the quantizer. This contribution shows some different methods to implement such ultra-broadband ADC front-ends. The first method, suitable for medium-resolution ADCs, is to use a track-hold-less analog front-end with a high-bandwidth input transconductor and a travelling-wave structure for the comparators of the quantizer. This input structure ensures proper alignment between the signal and the clock at all comparators. The method is illustrated by a 40GS/s 4-bit single-core flash-type BiCMOS ADC. For higher resolution ADCs, a linear front-end track-hold circuit is necessary, which can be implemented using a voltage-mode or a current-mode approach. The voltage-mode approach is exemplified by a 12GS/s BiCMOS circuit with track-mode masking and high SFDR in the first and second Nyquist band. The current mode approach is shown by a 25GS/s BiCMOS circuit with a 1dB input bandwidth of 40GHz. To reach even higher sampling rates, the analog input samples can be de-interleaved to several quantizers by means of an analog demultiplexer (ADeMUX). This is illustrated by a current-mode 1-to-4 ADeMUX implemented in BiCMOS running at 112GS/s.

Abstract

Today’s ultra-wideband optical equipment enables fiber-based data links with up to 1.6 Tbit/s per wavelength at a symbol rate of 128 Gbaud. However, high input signal path losses need to be overcome in commercial products when the digitizers are integrated with the digital signal processor in a deep-submicrometer FinFET-CMOS transceiver application specific integrated circuit (ASIC). This currently limits the analog-to-digital converter (ADC) sampling rate and the detectable link symbol rate to 97 GS/s and 66 Gbaud, respectively. Four of these bandwidth-limited ADCs can be time-interleaved with the presented analog 1-to-4 demultiplexer front end in a SiGe-BiCMOS technology that allows high bandwidths with transistor cutoff frequencies above 300 GHz. The sampling front end effectively divides the necessary ADC bandwidth by the time-interleaving factor, enabling the detection of ultra-high symbol rates of up to 128 Gbaud with only 16-GHz bandwidth requirement for the four ADCs. At these frequencies, subsequent circuits and chip interconnects exhibit significantly lower signal path losses than at 64 GHz—half the symbol rate—and therefore require only a reduced processing power for channel equalization in the analog and digital domain. We demonstrate sampling operation with a large-signal 3-dB bandwidth of 36 GHz and a 6-dB bandwidth of 50 GHz at 128 GS/s in an experimental testbed, as well as the reception of 128-Gbit/s NRZ/OOK and 256-Gbit/s PAM4 signals. The linearity reaches more than 3-bit effective number of bits (ENOB) with a sinusoidal input signal of 500 mV pp on each of the four output channels. The power consumption is equivalent to a sampling efficiency of 20 pJ/sample, narrowing the gap to slower CMOS solutions and enabling cost-efficient coherent optical links with up to 1 Tbit/s.

Abstract

In this paper the influence of dielectric loss induced noise on a differential charge detection system for cosmic dust trajectory sensors is analyzed. For the sake of generality the distributed charge detector is replaced by compact capacitors with different dielectric materials. It is shown that for low-frequency high-impedance systems the selection of very low loss dielectric materials is of crucial importance to minimize the overall noise charge of the system.

Abstract

A flexible and adaptive energy-efficient high-speed wireless hub is developed in polymer foil as a Hybrid System-in-Foil (HySiF) using Chip-Film Patch (CFP) technology. In this matter, the SiGe BiCMOS silicon chips (2.39 $\times$ 1.65 mm2) are thinned down to 45 mm and are embedded face-up inside a two-polymer CFP carrier. The active pads of the embedded silicon chips inside foil are extended to the surface of the foil to interconnect to the antenna on the foil. The integrated hybrid system has a signal transmission at 5--6 GHz frequency band. The overall thickness of the system is below 100 mm and its bendability is down to 4 mm radius of curvature. The designed and fabricated PA silicon chips operate at 50 mA with a 1.5 V supply voltage. Therefore, in addition to the high lateral thermal resistance of the thinned chip, self-heating loop inside polymer due to the low thermal conductivity of the embedding polymer raises the system temperature. Consequently, the thermal behavior and RF performance of the PA chip under different conditions are investigated. Moreover, the antenna with the required carrier frequency is simulated, fabricated, and measured on top of the polymer foil as a stand-alone system in the flexible CFP.

Abstract

High-speed analog-to-digital (ADC) and digital-to-analog converters (DAC) are key components for the core data network. As network traffic is still growing at an enormous rate, ultra-broadband converters are of uttermost importance. Especially the analog front-end section of these converters, i.e. the analog input of ADCs and the analog output of DACs, imposes severe challenges on the circuit design. SiGe-BiCMOS the technology of choice for the implementation of the these analog front ends, because SiGe bipolar transistors offer both extremely high cutoff frequencies needed for the converter bandwidth as well as large scale integration capability as needed for the complex converter circuitry. The EU/ECSEL project TARANTO does research on both the device speed enhancement as well as on advanced circuit topologies and designs for ultra-broadband analog front-end circuits for AD and DA conversion. This presentation will present solutions for implementing ultra-broadband ADC and DAC front-ends and discuss the main challenges for the corresponding circuit design. We will show practical circuit designs realized in TARANTO by URM1, USTUTT, USAAR and MICRAM as well as a test setup from NOKIA. For the data link receiver, we present very broadband SiGe BiCMOS analog front-end circuits for synchronous (STI) and asynchronous (ATI) time interleaving of AD converters. The STI front-end applies current mode integrating samplers whereas the ATI front-end applies mixers and filters. For the data link transmitter, an ultra-high-speed single-core SiGe BiCMOS DAC core will be shown. Moreover, we introduce the concept of D/A time interleaving with analog multiplexer circuits. Finally, we present a testbed for the test of a STI ADC front-end.