The Institute of Electrical and Optical Communications Engineering has developed a digital-to-analog converter with a conversion rate of 100 GS/s and 8 bit nominal resolution in a 28 nm low power CMOS technology. One possible application is in the field of coherent optical transmission systems.
The following figure shows a block diagram of the DAC. The DAC prototype converts 1-k symbols stored in the 1-kbyte on-chip memory cyclically.
The effective number of bits (ENOB) and spurious free dynamic range (SFDR) ranges from 5.3 bit and 41 dB to 3.2 bit and 27 dB from dc up to 24.9 GHz at 100 GS/s, respectively. The 3-dB bandwidth exceeds 13 GHz at 100 GS/s. The output signal roll off versus signal frequency is relatively flat resulting in 8 dB loss at 25 GHz including probes and cables to the 65 GHz bandwidth subsampling scope serving as a receiver.
- M. Grözing, H. Huang, X.-Q. Du, and M. Berroth, “Data converters for 100 Gbit/s communication links and beyond,” in Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SIRF). Digest of Papers, Austin, Texas, USA, 2016, pp. 104--106.
- H. Huang, J. Heilmeyer, M. Grözing, M. Berroth, J. Leibrich, and W. Rosenkranz, “An 8-bit 100-GS/s Distributed DAC in 28-nm CMOS for Optical Communications,” IEEE Transactions on Microwave Theory and Techniques, vol. 63, no. 4, pp. 1211--1218, 2015.
- H. Huang, J. Heilmeyer, M. Grözing, and M. Berroth, “An 8-bit 100-GS/s distributed DAC in 28-nm CMOS,” in IEEE Radio Frequency Integrated Circuits Symposium (RFIC), Tampa, FL, USA, 2014, pp. 65--68.