Digital-to-Analog-Converter with 100 GS/s

Digital-to-Analog-Converter with 100 GS/s in a 28 nm Low Power CMOS Technology

The Institute of Electrical and Optical Communications Engineering has developed a digital-to-analog converter with a conversion rate of 100 GS/s and 8 bit nominal resolution in a 28 nm low power CMOS technology. One possible application is in the field of coherent optical transmission systems.

The following figure shows a block diagram of the DAC. The DAC prototype converts 1-k symbols stored in the 1-kbyte on-chip memory cyclically.

100 GS/s DAC block diagram
100 GS/s DAC block diagram

The DAC is set up of two time-interleaved 50 GS/s NRZ-sub-DACs. Each NRZ-sub-DAC is again set up of two time-interleaved 25 GS/s RZ-DACs. With this concept, the output signal images are located beyond 75 GHz for signal frequencies up to 25 GHz.

100 GS/s DAC circuit & interleaving concept
DAC circuit & interleaving concept and image frequency shift beyond to 75 GHz.

The following figure shows a chip micrograph. The DAC chip has an area of 1.44 mm² and consumes 2.5 W. The distributed DAC output current summation network is implemented as an artificial transmission line to enhance the output bandwidth.

Chip micrograph with distributed output stage of the 100 GS/s DAC
Chip micrograph with distributed output stage of the 100 GS/s DAC

 The DAC chip was measured on both on-wafer and on an RF-PCB.

Packaging of the 100 GS/s DAc-chip on an RF-PCB with heatsink
Packaging of the 100 GS/s DAc-chip on an RF-PCB with heatsink

The effective number of bits (ENOB) and spurious free dynamic range (SFDR) ranges from 5.3 bit and 41 dB to 3.2 bit and 27 dB from dc up to 24.9 GHz at 100 GS/s, respectively. The 3-dB bandwidth exceeds 13 GHz at 100 GS/s. The output signal roll off versus signal frequency is relatively flat resulting in 8 dB loss at 25 GHz including probes and cables to the 65 GHz bandwidth subsampling scope serving as a receiver.

ENOB, SNDR and SFDR of the 100 GS/s DAC at 80 GS/s and 100 GS/s
ENOB, SNDR and SFDR of the 100 GS/s DAC at 80 GS/s and 100 GS/s

The following figure shows an on-wafer measurement result of one sub-DAC. The output frequency response enables open output PAM8 eyes at 40 Gbaud without and with 10% digital pre-emphasis, corresponding to an effective output data rate of 120 Gbit/s.

512-symbol PAM8 eye output signal at 40 Gbaud of one sub-DAC without (left) and with (right) 10% digital pre-emphasis.
512-symbol PAM8 eye output signal at 40 Gbaud of one sub-DAC without (left) and with (right) 10% digital pre-emphasis, resulting in 3x40 Gbaud x 3 bit/symbol = 120 Gbit/s effective output data rate.

The following figure shows a measurement result of one sub-DAC on a PCB. It shows an open PAM4 eye at 50 GS/s without and woth pre-emphasis. The effective output data rate is 100 Gbit/s.

512-symbol PAM4 eye ouput signal at 50 Gbaud without (left) and with (right) 10% digital pre-emphasis.
512-symbol PAM4 eye ouput signal at 50 Gbaud without (left) and with (right) 10% digital pre-emphasis. The effective data rate is 100 GS/s.

Publications

  1. 2016

    1. M. Grözing, H. Huang, X.-Q. Du, and M. Berroth, “Data converters for 100 Gbit/s communication links and beyond,” in Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SIRF). Digest of Papers, Austin, Texas, USA, 2016, pp. 104--106.

  2. 2015

    1. H. Huang, J. Heilmeyer, M. Grözing, M. Berroth, J. Leibrich, and W. Rosenkranz, “An 8-bit 100-GS/s Distributed DAC in 28-nm CMOS for Optical Communications,” IEEE Transactions on Microwave Theory and Techniques, vol. 63, no. 4, pp. 1211--1218, 2015.

  3. 2014

    1. H. Huang, J. Heilmeyer, M. Grözing, and M. Berroth, “An 8-bit 100-GS/s distributed DAC in 28-nm CMOS,” in IEEE Radio Frequency Integrated Circuits Symposium (RFIC), Tampa, FL, USA, 2014, pp. 65--68.
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Contact

This image shows Markus Grözing

Markus Grözing

Dr.-Ing.

Group Leader Integrated Circuits

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