This overview contains only the English lectures. For a complete overview, please switch to the German view.
Winter term 23/24
| Lecturers: | Dr.-Ing. Markus Grözing Univ.-Prof. Dr.-Ing. Georg Rademacher |
|---|---|
| Type: | Lecture |
| Sh: | 2 |
| Teaching Language: | English |
| Content: | The lecture Electronic Circuits repeats the main principals of linear time-invariant (LTI) electrical circuits as well as the very basics of analog transistors amplifiers and digital logic and memory circuits. Basic LTI circuit theory - voltages and currents in the basic elements R,L,C - Kirchhoff's laws - phasor method - nodal analysis - transfer function - two-port theory Active circuits: - Diode, MOSFET and BJT - basic analog amplifier circuits - CMOS logic circuits - registers and memory cells |
| Link: | C@MPUS |
| Lecturers: | Manuel Wittlinger Manfred Berroth |
|---|---|
| Type: | Lecture |
| Sh: | 2 |
| Teaching Language: | English/German |
| Content: | The lecture Mixed-Signal Integrated Circuits deals with analog and digital circuits for highest clock frequencies. The focus is on high-speed logic gates as well as A-D and D-A converters in integrated silicon bipolar technology. 1 Introduction 2 Bipolar Junction Transistor 2.1 Device Structure 2.2 Operating Regions, Characteristic Curves and DC Equivalent Circuits 2.2.1 Cut-off Region 2.2.2 Forward-active Region 2.2.3 Saturation Region 2.2.4 Reverse-active Region 2.2.5 Input and Output Characteristics 2.2.6 Direct Current Equivalent Circuits and Equations (Transport Model) 2.2.7 Gummel-Poon Plot 2.3 Second Order Effects 2.3.1 Base-width Modulation (Early Effect) 2.3.2 Breakdown Behaviour of the Bipolar Transistor 2.4 Dynamic Large Signal Behaviour of the Bipolar Transistor 2.4.1 Forward-active 2.4.2 Reverse-active 2.4.3 Charge-elements in the Dynamic Equivalent Circuit 2.5 Summary of the Transistor-equations (Transport Model) 2.5.1 NPN Transistor Equations 2.5.2 PNP Transistor Equations 2.6 Small Signal Behaviour of the Bipolar Transistor 2.7 Basic Circuits of the Bipolar Transistor 2.7.1 Common Emitter Configuration 2.7.2 Common Base Configuration 2.7.3 Common Collector Configuration, Emitter Follower 2.8 Example: Audio Frequency Amplifier in the Common Emitter Configuration 2.9 Example: Controlled Reference Oscillator (Colour Subcarrier Frequency) 2.10 Gummel-Poon Model 3 Basic Digital Circuits for High Frequency Operation 3.1 Saturated Bipolar Logic Circuits 3.1.1 Resistor-Transistor Logic (RTL) 3.1.2 Diode-Transistor Logic (DTL) 3.1.3 Transistor-Transistor Logic (TTL) 3.2 Unsaturated Bipolar Logic Circuits 3.2.1 Schottky-TTL 3.2.2 Current Mode Logic (CML) 3.2.3 Emitter Coupled Logic (ECL) 3.2.4 Supply Voltage for ECL Circuits 4 Components for Digital Signal Processing 4.1 Track-and-Hold Circuit 4.1.1 Deduction of the Setup Time tS on the Basis of a Simple Equivalent Circuit 4.1.2 Relations between Sampling Frequency, Resolution and Time Constant τt0 4.1.3 Relations between Maximum Signal Frequency, Resolution and Aperture Jitter ΔtA 4.1.4 Effects of the Aperture Jitter on the SNR 4.1.5 Example Circuits 4.2 Analog to Digital Converter (ADC) 4.2.1 Flash Converter 4.2.2 Successive Approximation Converters 4.2.3 Delta Converter and Delta Sigma Converter 4.3 Digital to Analog Converter (DAC) 4.4 Time-Interleaving 4.5 Current Sources 4.5.1 Wilson Current Source 4.6 Bandgap Reference Circuits 5 Selected Nonlinear Circuits 5.1 3R-Regeneration in Digital Systems 5.2 Phase-Locked Loop (PLL) 5.2.1 Linear PLL 5.2.2 Digital PLL 5.3 Multiplexer and Demultiplexer 5.4 Direct Digital Synthesis (DDS) 5.5 Protective Structures for CMOS Input Pads 6 Other Field-Effect Transistors 6.1 Compound Semiconductors 6.2 MESFET Structure and Current Equations 6.3 MESFET Small Signal Equivalent Circuit 6.4 HFET (Heterojunction Field-Effect Transistor) 6.5 DCFL (Direct-Coupled FET Logic) 6.5.1 DCFL-Inverter 6.5.2 DCFL Logic Elements 7 Comparison between Bipolar- and CMOS-Technology 7.1 Digital Circuits 7.2 Analog Circuits |
| Link: | C@MPUS |
| Lecturers: | Manuel Wittlinger Manfred Berroth |
|---|---|
| Type: | Exercise |
| Sh: | 2 |
| Teaching Language: | English/German |
| Content: | In the exercises the knowledge from the lectures is used for calculations on practical examples. Dimensioning and analysis of several circuits is done. Exercise 1 Simple Inverter with Bipolar Transistor Exercise 2 Amplifier Circuit with Stabilized Operating Point Exercise 3 Basic CML Circuit Exercise 4 Modified ECL Circuit Exercise 5 ECL Circuit Exercise 6 Track-and-Hold Circuit with Switched Emitter Follower Exercise 7 Analog-to-Digital Converter With Bipolar Differential Amplifier Exercise 8 SAR Converter Exercise 9 Digital-to-Analog Converter Circuit Exercise 10 Constant Current Source and Digital-to-Analog Converter Exercise 11 Bandgap Voltage Reference Circuit Exercise 12 Wilson Current Mirror Exercise 13 Phase-Locked Loop With Phase Detector |
| Link: | C@MPUS |
| Lecturers: | Univ.-Prof. Dr.-Ing. Georg Rademacher |
|---|---|
| Type: | Lecture |
| Sh: | 2 |
| Teaching Language: | English/German |
| Content: | Fundamentals of optical communications: Plane waves, dispersion, attenuation, reflection • Optical fibers: Fiber modes, single and multi-mode fibers, multi-core fibers, fiber manufacturing, coupling • Light sources: Semiconductor lasers • Signal generation: directly modulated lasers, external modulators, IQ modulators • Optical receivers: Photo diodes, receivers for direct detection, coherent receivers • Optical amplification: EDFAs, noise • Optical transmission systems: noise analysis, bit-error rates, optical signal to noise ratio, nonlinear signal distortions, Digital signal processing, capacity limitations • Current research in optical fiber transmission: space-division multiplexing, integrated optics, and more! |
| Link: | C@MPUS |
Contact information for the lecturers can be found on our team page.
Summer term 23
| Lecturers: | Manfred Berroth |
|---|---|
| Type: | Lecture |
| Sh: | 2 |
| Teaching Language: | English |
| Content: | TABLE OF CONTENTS 1. INTRODUCTION 1.1 Glossary of terms 2. VLSI DESIGN STYLES AND COST ESTIMATION 2.1 Design styles 2.2 Cost estimation 3. TECHNOLOGIES FOR INTEGRATED CIRCUITS 3.1 Important manufacturing processes .....3.1.1 Epitaxy .....3.1.2 Photolithography and mask fabrication .....3.1.3 Deposition of material .....3.1.4 Etching process .....3.1.5 Diffusion and implantation 3.2 N-well CMOS process 3.3 High-k metal gate 3.4 Design rules .....3.4.1 Geometrical design rules .....3.4.2 Electrical design rules 3.5 Parasitic elements .....3.5.1 Parasitic resistance .....3.5.2 Parasitic capacitance .....3.5.3 Parasitic inductance .....3.5.4 Parasitic conductance 3.6 Transmission lines .....3.6.1 RC model .....3.6.2 RLGC model .....3.6.3 Transmission line designs .........3.6.3.1 Microstrip .........3.6.3.2 Coplanar 4. DESIGN TOOLS 4.1 Mask design .....4.1.1 Floorplanning .....4.1.2 Placement .....4.1.3 Routing 4.2 Mask layout verification .....4.2.1 Design rule check (DRC) .....4.2.2 Layout parasitic extraction (LPE) .....4.2.3 Electrical rule checker (ERC) .....4.2.4 Layout versus schematic (LVS) .....4.2.5 Automatic mask design generation 4.3 Circuit simulator: SPICE, Spectre, ADS 4.4 Timing simulation 4.5 Logic simulation 5. TESTING OF INTEGRATED CIRCUITS 5.1 Types of faults 5.2 Test vector generation .....5.2.1 Comprehensive test .....5.2.2 Five-valued logic .....5.2.3 D-algorithm .....5.2.4 Signal controllability and observability 5.3 Methods for increasing testability .....5.3.1 Ad-hoc testing .....5.3.2 Structured design for testing with scan paths .....5.3.3 Built-in-self-test (BIST) 6. CLOCK DISTRIBUTION AND ASYNCHRONOUS NETWORKS 6.1 Synchronous clock systems 6.2 Asynchronous circuits 6.3 Synchronization 7. HIGHEST PERFORMANCE CIRCUITS AND SYSTEMS 7.1 Alternative binary logic family 7.2 Comparison of dissipation loss of DCFL and CMOS logic circuits 7.3 Multilevel circuits 7.4 Efficiency comparison of circuit architectures .....7.4.1 Efficiency of a simple arithmetic logic unit .....7.4.2 Parallel partial arithmetic logic units .....7.4.3 Parallel arithmetic logic units .....7.4.4 Serial partial arithmetic logic units .....7.4.5 Pipeline arithmetic logic units 8. DESIGN FOR MANUFACTURABILITY (STATISTICAL DESIGN) 8.1 Basic concepts and definitions 8.2 Layout rules for mismatch reduction .....8.2.1 Identical structures .....8.2.2 Identical temperatures .....8.2.3 Same size and orientation .....8.2.4 Minimum distance between identical devices .....8.2.5 Common centroid layout .....8.2.6 Same environment by using dummy devices .....8.2.7 Avoidance of minimum device structures |
| Link: | C@MPUS |
| Lecturers: | Sefa Özbek Manfred Berroth |
|---|---|
| Type: | Exercise |
| Sh: | 2 |
| Teaching Language: | English |
| Content: | This course provides fundamental and advanced examples for the physical design of integrated CMOS circuits. Carefully selected exercises aim to familiarise students with the theory and practice of application-specific IC design from schematic to layout to full physical verification for chip fabrication. More information about the course topics can be found here: https://campus.uni-stuttgart.de/cusonline/LV.edit?clvnr=223590. |
| Link: | C@MPUS |