This overview contains only the English lectures. For a complete overview, please switch to the German view.
Winter term 24/25
| Number: | 372102510 |
|---|---|
| Lecturers: | Dr.-Ing. Markus Grözing Manuel Wittlinger |
| Type: | Lecture |
| Sh: | 2 |
| Teaching Language: | English/German |
| Content: | Preliminary Contents Mixed-Signal Integrated Circuits (MSIC) Mixed-signal circuits contain both analogue and digital circuits as well as the necessary circuits for the transition from one signal domain to the other, i.e. analogue-to-digital as well as digital-to-analogue converters. 1. Introduction 1.1. Overview MSIC 1.2. Signal Domains (Continuous vs Discrete Time / Value) 1.3. Signal Quality Measures (SFDR, THD, SNR, SNDR/ENOB) 1.4. Transistor Device Recapitulation (MOSFET & BJT) 2. Basic Analog and Digital Circuit Recapitulation 2.1. Basic Analog Circuits 2.1.1. Basic Amplifiers 2.1.2. Differential / Emitter-/Source-Coupled Pairs 2.1.3. Current Sources & Switches 2.1.4. Feedback for Broadband & Linear Amplifiers / Buffers 2.1.5. Bandgap Voltage Reference 2.2. Basic Digital Circuits 2.2.1. CMOS Logic & Latches 2.2.2. Current-Mode Logic / Emitter-/Source-Coupled Logic & Latches 3. Basic Mixed Signal Circuit Blocks (Signal Domain Interface) 3.1. Track & Hold Circuits 3.2. Comparators (Compare & Decide + Regenerate) 3.3. Resistive and Capacitive Weighting Networks (R-2R, SC) 4. Data Converter Design Introduction 4.1. Analog-to-Digital Converter (ADC) 4.1.1. Overview ADC Architectures 4.1.2. Basic Flash Converter (Resistor Ladder, Quantizer, Coder) 4.2. Digital-to- Analog Converter (DAC) 4.2.1. Overview DAC Architectures 4.2.2. Basic Switched Current-Source Converter (Current Sources, Current Switches, R-2R weighting network) |
| Link: | C@MPUS |
| Number: | 372102520 |
|---|---|
| Lecturers: | Dr.-Ing. Markus Grözing Manuel Wittlinger |
| Type: | Exercise |
| Sh: | 2 |
| Teaching Language: | English/German |
| Content: | In the exercises the knowledge from the lecture Mixed-Signal Integrated Circuits (MSIC) is used for calculations on practical examples. Dimensioning and analysis of several circuits is done. |
| Link: | C@MPUS |
| Number: | 372113510 |
|---|---|
| Lecturers: | Univ.-Prof. Dr.-Ing. Georg Rademacher Raik Elster |
| Type: | Lecture |
| Sh: | 2 |
| Teaching Language: | English/German |
| Content: | Fundamentals of optical communications: Plane waves, dispersion, attenuation, reflection • Optical fibers: Fiber modes, single and multi-mode fibers, multi-core fibers, fiber manufacturing, coupling • Light sources: Semiconductor lasers • Signal generation: directly modulated lasers, external modulators, IQ modulators • Optical receivers: Photo diodes, receivers for direct detection, coherent receivers • Optical amplification: EDFAs, noise • Optical transmission systems: noise analysis, bit-error rates, optical signal to noise ratio, nonlinear signal distortions, Digital signal processing, capacity limitations • Current research in optical fiber transmission: space-division multiplexing, integrated optics, and more! |
| Link: | C@MPUS |
| Number: | 372113520 |
|---|---|
| Lecturers: | Univ.-Prof. Dr.-Ing. Georg Rademacher Raik Elster |
| Type: | Exercise |
| Sh: | 2 |
| Teaching Language: | English/German |
| Link: | C@MPUS |
Contact information for the lecturers can be found on our team page.
Summer term 23
| Lecturers: | Prof. Dr.-Ing. Manfred Berroth |
|---|---|
| Type: | Lecture |
| Sh: | 2 |
| Teaching Language: | English |
| Content: | TABLE OF CONTENTS 1. INTRODUCTION 1.1 Glossary of terms 2. VLSI DESIGN STYLES AND COST ESTIMATION 2.1 Design styles 2.2 Cost estimation 3. TECHNOLOGIES FOR INTEGRATED CIRCUITS 3.1 Important manufacturing processes .....3.1.1 Epitaxy .....3.1.2 Photolithography and mask fabrication .....3.1.3 Deposition of material .....3.1.4 Etching process .....3.1.5 Diffusion and implantation 3.2 N-well CMOS process 3.3 High-k metal gate 3.4 Design rules .....3.4.1 Geometrical design rules .....3.4.2 Electrical design rules 3.5 Parasitic elements .....3.5.1 Parasitic resistance .....3.5.2 Parasitic capacitance .....3.5.3 Parasitic inductance .....3.5.4 Parasitic conductance 3.6 Transmission lines .....3.6.1 RC model .....3.6.2 RLGC model .....3.6.3 Transmission line designs .........3.6.3.1 Microstrip .........3.6.3.2 Coplanar 4. DESIGN TOOLS 4.1 Mask design .....4.1.1 Floorplanning .....4.1.2 Placement .....4.1.3 Routing 4.2 Mask layout verification .....4.2.1 Design rule check (DRC) .....4.2.2 Layout parasitic extraction (LPE) .....4.2.3 Electrical rule checker (ERC) .....4.2.4 Layout versus schematic (LVS) .....4.2.5 Automatic mask design generation 4.3 Circuit simulator: SPICE, Spectre, ADS 4.4 Timing simulation 4.5 Logic simulation 5. TESTING OF INTEGRATED CIRCUITS 5.1 Types of faults 5.2 Test vector generation .....5.2.1 Comprehensive test .....5.2.2 Five-valued logic .....5.2.3 D-algorithm .....5.2.4 Signal controllability and observability 5.3 Methods for increasing testability .....5.3.1 Ad-hoc testing .....5.3.2 Structured design for testing with scan paths .....5.3.3 Built-in-self-test (BIST) 6. CLOCK DISTRIBUTION AND ASYNCHRONOUS NETWORKS 6.1 Synchronous clock systems 6.2 Asynchronous circuits 6.3 Synchronization 7. HIGHEST PERFORMANCE CIRCUITS AND SYSTEMS 7.1 Alternative binary logic family 7.2 Comparison of dissipation loss of DCFL and CMOS logic circuits 7.3 Multilevel circuits 7.4 Efficiency comparison of circuit architectures .....7.4.1 Efficiency of a simple arithmetic logic unit .....7.4.2 Parallel partial arithmetic logic units .....7.4.3 Parallel arithmetic logic units .....7.4.4 Serial partial arithmetic logic units .....7.4.5 Pipeline arithmetic logic units 8. DESIGN FOR MANUFACTURABILITY (STATISTICAL DESIGN) 8.1 Basic concepts and definitions 8.2 Layout rules for mismatch reduction .....8.2.1 Identical structures .....8.2.2 Identical temperatures .....8.2.3 Same size and orientation .....8.2.4 Minimum distance between identical devices .....8.2.5 Common centroid layout .....8.2.6 Same environment by using dummy devices .....8.2.7 Avoidance of minimum device structures |
| Link: | C@MPUS |
| Lecturers: | Prof. Dr.-Ing. Manfred Berroth Sefa Özbek |
|---|---|
| Type: | Exercise |
| Sh: | 2 |
| Teaching Language: | English |
| Content: | This course provides fundamental and advanced examples for the physical design of integrated CMOS circuits. Carefully selected exercises aim to familiarise students with the theory and practice of application-specific IC design from schematic to layout to full physical verification for chip fabrication. More information about the course topics can be found here: https://campus.uni-stuttgart.de/cusonline/LV.edit?clvnr=223590. |
| Link: | C@MPUS |