Folding- and Interpolating Analog-to-Digital-Converter

Folding- and Interpolating Analog-to-Digital-Converter for 6.4 GS/s and 12.1 GS/s with 9.5 bit resolution

High data rates and bandwidths are very important in high-end applications like radio frequency measurement. However, these requirements can significantly decrease the linearity of the employed circuits. Furthermore, particularly CMOS circuits can process only small input voltage ranges at high data rates. This can be a major disadvantage, e.g. in radio frequency oscilloscopes.

Silicon-Germanium hetero bipolar transistors have great benefits in these applications. They work with higher voltage ranges and at the same time higher switching frequencies than CMOS technologies. Best results can be achieved with an integration of both, where they can show their individual advantages together. Therefore, we use various of such modern BiCMOS technologies for the design of very fast and broadband data converter front-ends with high linearity. The transistors can show transit frequencies of up to 320 GHz at the moment.

Am example of such a Track-and-Hold circuit with a conversion rate of 6.4 GS/s and a nominal resolution of 9.5 bit with 2 Vpp differential input voltage range and 50 dBc dynamic range is shown in the following figure. It can be used for parallelization of data converters with lower sampling rates to vastly improve the performance e.g. of radio frequency sensors.

Circuit diagram of a 6 GS/s Track-and-Hold circuit
Circuit diagram of a 6 GS/s Track-and-Hold circuit

The realization is done in a 0.25 µm SiGe-BiCMOS technology.

Chip photograph of a 6 GS/s Track-and-Hold circuit
Chip photograph of a 6 GS/s Track-and-Hold circuit

In a follow-up project, folding and interpolation converters are addressed at a conversion rate of 12.1 GS/s. By using a modern 55 nm SiGe BiCMOS technology, the performance can be significantly reduced despite doubling the conversion rate.

Publications

  1. 2016

    1. M. Buck, M. Grözing, R. Bieg, J. Digel, X.-Q. Du, P. Thomas, M. Berroth, M. Epp, J. Rauscher, and M. Schlumpp, “A 6 GS/s 9.5 bit pipelined folding-interpolating ADC with 7.3 ENOB and 52.7 dBc SFDR in the 2nd Nyquist band in 0.25 µm SiGe-BiCMOS,” in IEEE Radio Frequency Integrated Circuits Symposium (RFIC), San Francisco, CA, USA, 2016, pp. 15--18.
  2. 2013

    1. M. Buck, M. Grözing, M. Berroth, M. Epp, and S. Chartier, “A 6 GHz input bandwidth 2 Vpp-diff input range 6.4 GS/s track-and-hold circuit in 0.25 mm BiCMOS,” in IEEE Radio Frequency Integrated Circuits Symposium (RFIC), Seattle, WA, USA, 2013, pp. 159--162.

Contact

This image shows Markus Grözing

Markus Grözing

Dr.-Ing.

Group Leader Integrated Circuits

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