INT Forschung aktuell

2. Juni 2022 / INT

Das INT stellt zwei Paper auf dem International Symposium on Circuits and Systems 2022 vor.
[Bild: www.iscas2022.org]

Mixed-Signal Integrated Circuit for Direct Raised-Cosine Filter Waveform Synthesis of Digital Signals Up to 24 GS/s in 22 nm FD-SOI CMOS Technology

Daniel Widmann, Raphael Nägele, Markus Grözing, Manfred Berroth

Abstract — Pulse shaping for signal transmission over bandwidth limited channels and for sensor systems is very important to control intersymbol interference and to comply with spectrum emission mask specifications by reducing the occupied bandwidth. In this work, an efficient, low-power concept for digital-to-waveform conversion is presented on a 22nm CMOS node. A key characteristic is the approximation concept of a raised-cosine filter for waveform synthesis by non-binary weighting in the digital-to-analog converter (DAC) keeping hardware complexity and thus power consumption low. Due to the proposed pulse shaping method, spectral side lobes of a pseudo-random bit stream example can be reduced by more than 20 dB at 24 GS/s and a power consumption of only about 30mW. In summary, this concept replaces high-resolution DACs or analog filters, respectively, in pulse shaping circuits by simple CMOS logic and an application-centric DAC.

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Integrating Ultra-Thin SiGe BiCMOS Power Amplifier Chip in Combination with Flexible Antenna in the Polymer Foil

Sefa Özbek1, Shuo Wang2, Serafin B. Fischer3, Markus Grözing1, Joachim N. Burghartz2, Jan Hesselbarth3, Manfred Berroth1
1Inst. of Electrical and Optical Communications Engineering, University of Stuttgart, Germany
2Inst. of Nano and Microelectronic Systems, University of Stuttgart, Germany
3Inst. of Radio Frequency Technology, University of Stuttgart, Germany

Abstract — In this work, a mechanically flexible and high-speed transmitter front-end system is presented as a hybrid System-in-Foil (HySiF) by combining Chip-Film Patch (CFP) technology, a bow-tie dipole antenna, and cost-effective 0.25 μm SiGe:C BiCMOS class-A mode power amplifier (PA) in a single compelling field. For the matter of a flexible system, the silicon (Si) chip is thinned down to 38 μm to be embedded into the polymer CFP carrier. For the sake of facilitating the thermal management of the die, an AlSiCu heat spreader is added underneath the thin silicon chip, thereby reducing the predicted temperature rise due to the self -heating loop inside the polymer. The measured gain center frequency of the PA with the ultra-thin silicon substrate shifts about 300 MHz towards higher frequencies due to the eddy current within the AlSiCu plate heat spreader at the backside of the chip. For that purpose, thermal behavior and RF performance of the system w.r.t. the different heat spreader structures are investigated. In addition, the pads of the embedded silicon chip are interconnected to the bow-tie dipole antenna by using a metal layer of AlSiCu through via openings on the foil.

Projektseite

 

Institut für Elektrische und Optische Nachrichtentechnik

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