Bit rate flexible sampling equalizer

Data rates on backplanes, over memory interfaces and over on-chip modules have already reached several Gbit/s nowadays and are increasing continuously. 10 Gbit/s are transmitted in today’s wide area optical nets and systems with 40 Gbit/s per channel are near commercialization. Intersymbol interference in the received data stream is an increasingly severe problem for such high-speed links. As low loss PCB substrates and optical dispersion compensators are expensive, electronic predistortion or receive-equalization are an advantageous alternative.

A bit-rate flexible receive equalizer for data rates up to 10 Gbit/s is presented here. The circuit processes discrete-time analogue samples of the incoming signal. The equalizer combines a discrete-time FIR-filter with 3 taps and a decision feedback equalizer with two feedback paths. The FIR-filter uses track-and-hold circuits as delay elements for full bit-rate flexibility. The whole filter is implemented in a half-rate structure to circumvent the use of peaking inductors. The presented equalizer occupies a small chip area, is low-power and has a small latency. Thus, it can be used in massive parallel links like the memory interface. the chip is produced in a 130 nm CMOS technology.