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Fast and efficient analog processor for AI accelerators and optical data links

Application of energy-efficient high-speed electronic analog arithmetic circuits in artificial neural networks for AI accelerators and in transmitters and receivers of optical data links for the compensation of linear and non-linear distortions.

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The enormous performance of artificial intelligence for various problems is leading to its use in more and more applications and has triggered a veritable boom, particularly with the introduction of ChatGPT. Such systems are based on artificial neural networks for whose inference the two arithmetic operations multiplication and addition are essentially calculated billions of times. 

Optical data link with analog ANN in the receiver to compensate for the chromatic dispersion of the optical fibre.
Optical data link with analog ANN in the receiver to compensate for the chromatic dispersion of the optical fibre.

In conventional digital arithmetic units, many hundreds of MOSFETs are used for the simple multiplication of two numbers in so-called field multipliers and are recharged for each calculation, which consumes a lot of energy during the calculation. This is where INT's new analog computing circuit concept comes in, which was developed as part of the BMBF-funded AI-NET research project. The analog two-quadrant multiplier only requires two field-effect transistors. Current flows through these for only a very brief moment, whereby the multiplication result, mapped as an electrical charge, is calculated. No additional component is even required for the addition, as the physical principle of Kirchhoff's node rule is utilized here. This results in a very large potential for increasing efficiency. Arithmetic units for AI applications on computer chips in data centers and smartphones as well as transmitter and receiver circuits for optical data transmission could thus become significantly smaller and more energy-efficient. Previous studies indicate that analogue multiplication with the new INT technology is around 100 times more energy-efficient than an already greatly reduced and optimized digital FP4 multiplication on the latest generation of Nvidia AI accelerators (GPU Blackwell GB200).

Test chip for the analog AI accelerator in 22nm CMOS technology.
Test chip for the analog AI accelerator in 22nm CMOS technology.
Photo: University of Stuttgart - INT

In the project, two ASICs in a 22 nm FDSOI CMOS technology were developed, which confirm the basic functionality of the analog computing cells as well as the low energy consumption through measurement characterization.
The figure shows the second designed ASIC on which several neuronal layers based on the analog computing cells are implemented.

This project is funded by the BMBF under the funding code 16KIS1313
This project is funded by the BMBF under the funding code 16KIS1313
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Publications

  1. 2024

    1. J. Finkbeiner, R. Nägele, M. Grözing, M. Berroth, and G. Rademacher, “Ultra-energy-efficient analog multiply-accumulate and rectified linear unit circuit for artificial neural network inference accelerators,” in International Conference on Neuromorphic Computing and Engineering 2024 (ICNCE), 2024.
    2. J. Finkbeiner, R. Nägele, M. Grözing, M. Berroth, and G. Rademacher, “Characterization of a Femtojoule Voltage-to-Time Converter with Rectified Linear Unit Characteristic for Analog Neural Network Inference Accelerators,” in IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS), 2024, p. accepted.
    3. R. Nägele, J. Finkbeiner, M. Grözing, M. Berroth, and G. Rademacher, “Characterization of an Analog MAC Cell with Multi-Bit Resolution for AI Inference Accelerators,” in IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS), 2024, p. accepted.

  2. 2023

    1. R. Nägele, J. Finkbeiner, V. Stadtlander, M. Grözing, and M. Berroth, “Analog Multiply-Accumulate Cell with Multi-Bit Resolution for All-Analog AI Inference Accelerators,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 2023, pp. 1--13, 2023.

  3. 2022

    1. J. Finkbeiner, R. Nägele, M. Berroth, and M. Grözing, “Design of an Energy Efficient Voltage-to-Time Converter with Rectified Linear Unit Characteristics for Artificial Neural Networks,” in IEEE International New Circuits and Systems Conference (NEWCAS), 2022, pp. 327--331.
    2. R. Nägele, J. Finkbeiner, M. Berroth, and M. Grözing, “Design of an Energy Efficient Analog Two-Quadrant Multiplier Cell Operating in Weak Inversion,” in IEEE International New Circuits and Systems Conference (NEWCAS), 2022, pp. 5--9.
Additional Information

Contact

Jakob Finkbeiner

M. Sc.

Research staff member

Raphael Nägele

M. Sc.

Research staff member

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