Fast and efficient analog processor for optical data links

Integrated analog arithmetic units for ANN applications offer the potential of significantly higher energy and area efficiency compared to classical binary arithmetic units. However, in analogue circuits, computational accuracy is degraded by noise, nonlinearities and mismatch. Furthermore, traditional analogue signal processing circuits in class A operation are not very energy efficient. In this research project, new concepts for energy-efficient high-speed analog arithmetic circuits in an advanced FDSOI CMOS technology are explored and adapted for broadband optical data links.

First, the performance, energy efficiency, accuracy, stability and possible degree of integration of different analog arithmetic circuit concepts will be investigated and evaluated. Then, a specific analogue ANN equaliser circuit for a specific partial function of a transmit or receive ASIC in an optical data link is designed, fabricated and characterized. Finally, the developed circuit is evaluated in terms of its applicability, scalability and performance in ANN-based transmitters and receivers for optical data networks and compared with digital approaches.