Fast and efficient analog processor for AI accelerators and optical data links

In conventional digital arithmetic units, many hundreds of MOSFETs are used for the simple multiplication of two numbers in so-called field multipliers and are recharged for each calculation, which consumes a lot of energy during the calculation. This is where INT's new analog computing circuit concept comes in, which was developed as part of the BMBF-funded AI-NET research project. The analog two-quadrant multiplier only requires two field-effect transistors. Current flows through these for only a very brief moment, whereby the multiplication result, mapped as an electrical charge, is calculated. No additional component is even required for the addition, as the physical principle of Kirchhoff's node rule is utilized here. This results in a very large potential for increasing efficiency. Arithmetic units for AI applications on computer chips in data centers and smartphones as well as transmitter and receiver circuits for optical data transmission could thus become significantly smaller and more energy-efficient. Previous studies indicate that analogue multiplication with the new INT technology is around 100 times more energy-efficient than an already greatly reduced and optimized digital FP4 multiplication on the latest generation of Nvidia AI accelerators (GPU Blackwell GB200).

In the project, two ASICs in a 22 nm FDSOI CMOS technology were developed, which confirm the basic functionality of the analog computing cells as well as the low energy consumption through measurement characterization.
The figure shows the second designed ASIC on which several neuronal layers based on the analog computing cells are implemented.