Raphael Nägele

M. Sc.

Research staff member
Institute of Electrical and Optical Communications
IC group

Contact

+49 711 685 69191
 +49 711 685 67900
Business card (VCF)

Pfaffenwaldring 47
70569 Stuttgart
Deutschland
Room: 2.408

Subject

My field of activity includes research on energy-efficient mixed-signal neurons for artificial neural networks. Artificial neural networks have in recent years experienced an increasing spread. For decentralized use, where the computing power and the resulting power consumption is very limited, new hardware implementations are therefore required. A promising approach to increase efficiency is the analog instead of the usual digital processing of signals in the neural network.
The research work covers the design of mixed-signal neurons as well as the periphery needed for the inference of a network. Furthermore, such neural networks are investigated with respect to their trainability.

In addition, I am involved in a research association with the Institute for Robust Power Semiconductor Systems (ILH), which deals with the design of high-frequency radar systems in a 22 nm technology. Potential applications are driving assistance systems of vehicles, which are especially important for autonomous driving.

  1. 2026

    1. J. Finkbeiner, R. Nägele, M. Grözing, M. Berroth, and G. Rademacher, “A 0.6 pJ/bit Analog Equalizer ASIC for Nonlinearity Compensation in IM/DD Links,” in Optical Fiber Communication Conference (OFC), 2026, p. accepted.

  2. 2025

    1. M. Grözing, R. Nägele, J. Finkbeiner, and G. Rademacher, “Two-path operational amplifier using FDSOI CMOS with first fast low-gain and second slow high-gain path for fast regulated voltage buffers with low offset error,” in Analog Workshop, 2025, pp. 26–29.
    2. J. Finkbeiner, R. Nägele, M. Wittlinger, M. Grözing, M. Berroth, and G. Rademacher, “PANNA: A 558 TOPS/W Pipelined All-Analog Neural Network Accelerator in 22 nm FD-SOI,” IEEE Solid-State Circuits Letters, pp. 1–4, 2025.
    3. J. Finkbeiner, R. Nägele, M. Wittlinger, M. Grözing, M. Berroth, and G. Rademacher, “Analoge Berechnung von Künstlichen Neuronalen Netzen in 22 nm FD-SOI CMOS,” in Analog Workshop, 2025, pp. 18–19.
    4. M. Wittlinger, J. Finkbeiner, R. Nägele, M. Grözing, M. Berroth, and G. Rademacher, “Glitch-freier, jitterarmer Amplituden- und Phasenschalter für digitale RF-Pulsmodulation,” in Analog Workshop, 2025, pp. 43–44.

  3. 2024

    1. J. Finkbeiner, R. Nägele, M. Grözing, M. Berroth, and G. Rademacher, “Characterization of a Femtojoule Voltage-to-Time Converter with Rectified Linear Unit Characteristic for Analog Neural Network Inference Accelerators,” in IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS), 2024, pp. 253–257.
    2. J. Finkbeiner, R. Nägele, M. Grözing, M. Berroth, and G. Rademacher, “Ultra-energy-efficient analog multiply-accumulate and rectified linear unit circuit for artificial neural network inference accelerators,” in International Conference on Neuromorphic Computing and Engineering 2024 (ICNCE), 2024.
    3. R. Nägele, J. Finkbeiner, M. Grözing, M. Berroth, and G. Rademacher, “Characterization of an Analog MAC Cell with Multi-Bit Resolution for AI Inference Accelerators,” in IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS), 2024, pp. 243–247.

  4. 2023

    1. R. Nägele, J. Finkbeiner, V. Stadtlander, M. Grözing, and M. Berroth, “Analog Multiply-Accumulate Cell with Multi-Bit Resolution for All-Analog AI Inference Accelerators,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 2023, pp. 1–13, 2023.

  5. 2022

    1. D. Widmann, R. Nägele, M. Grözing, and M. Berroth, “Mixed-Signal Integrated Circuit for Direct Raised-Cosine Filter Waveform Synthesis of Digital Signals Up to 24 GS/s in 22 nm FD-SOI CMOS Technology,” in IEEE International Symposium on Circuits and Systems (ISCAS), 2022, p. paper ID 1248.
    2. J. Finkbeiner, R. Nägele, M. Berroth, and M. Grözing, “Design of an Energy Efficient Voltage-to-Time Converter with Rectified Linear Unit Characteristics for Artificial Neural Networks,” in IEEE International New Circuits and Systems Conference (NEWCAS), 2022, pp. 327–331.
    3. R. Nägele, J. Finkbeiner, M. Berroth, and M. Grözing, “Design of an Energy Efficient Analog Two-Quadrant Multiplier Cell Operating in Weak Inversion,” in IEEE International New Circuits and Systems Conference (NEWCAS), 2022, pp. 5–9.

  6. 2021

    1. D. Widmann, R. Nägele, and A. Gatzastras, “140 GHz Transmitter Chip for Pseudo Random Noise Radar in 22 nm FD-SOI CMOS Technology,” in EUROPRACTICE activity report 2020 - 2021, 2021, p. 22.
    2. R. Nägele, F. Wiewel, S. Kelz, M. Wittlinger, M. Berroth, B. Yang, and M. Grözing, “Charge based mixed-signal multiply-accumulate circuit for energy efficient in-memory computing,” in Kleinheubacher Tagung, U.R.S.I. Landesausschuss in der Bundesrepublik Deutschland e.V, 2021, pp. 1–4.
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