Jakob Finkbeiner

Abstract

Today’s ultra-wideband optical equipment enables fiber-based data links with up to 1.6 Tbit/s per wavelength at a symbol rate of 128 Gbaud. However, high input signal path losses need to be overcome in commercial products when the digitizers are integrated with the digital signal processor in a deep-submicrometer FinFET-CMOS transceiver application specific integrated circuit (ASIC). This currently limits the analog-to-digital converter (ADC) sampling rate and the detectable link symbol rate to 97 GS/s and 66 Gbaud, respectively. Four of these bandwidth-limited ADCs can be time-interleaved with the presented analog 1-to-4 demultiplexer front end in a SiGe-BiCMOS technology that allows high bandwidths with transistor cutoff frequencies above 300 GHz. The sampling front end effectively divides the necessary ADC bandwidth by the time-interleaving factor, enabling the detection of ultra-high symbol rates of up to 128 Gbaud with only 16-GHz bandwidth requirement for the four ADCs. At these frequencies, subsequent circuits and chip interconnects exhibit significantly lower signal path losses than at 64 GHz—half the symbol rate—and therefore require only a reduced processing power for channel equalization in the analog and digital domain. We demonstrate sampling operation with a large-signal 3-dB bandwidth of 36 GHz and a 6-dB bandwidth of 50 GHz at 128 GS/s in an experimental testbed, as well as the reception of 128-Gbit/s NRZ/OOK and 256-Gbit/s PAM4 signals. The linearity reaches more than 3-bit effective number of bits (ENOB) with a sinusoidal input signal of 500 mV pp on each of the four output channels. The power consumption is equivalent to a sampling efficiency of 20 pJ/sample, narrowing the gap to slower CMOS solutions and enabling cost-efficient coherent optical links with up to 1 Tbit/s.

Abstract

High-speed analog-to-digital (ADC) and digital-to-analog converters (DAC) are key components for the core data network. As network traffic is still growing at an enormous rate, ultra-broadband converters are of uttermost importance. Especially the analog front-end section of these converters, i.e. the analog input of ADCs and the analog output of DACs, imposes severe challenges on the circuit design. SiGe-BiCMOS the technology of choice for the implementation of the these analog front ends, because SiGe bipolar transistors offer both extremely high cutoff frequencies needed for the converter bandwidth as well as large scale integration capability as needed for the complex converter circuitry. The EU/ECSEL project TARANTO does research on both the device speed enhancement as well as on advanced circuit topologies and designs for ultra-broadband analog front-end circuits for AD and DA conversion. This presentation will present solutions for implementing ultra-broadband ADC and DAC front-ends and discuss the main challenges for the corresponding circuit design. We will show practical circuit designs realized in TARANTO by URM1, USTUTT, USAAR and MICRAM as well as a test setup from NOKIA. For the data link receiver, we present very broadband SiGe BiCMOS analog front-end circuits for synchronous (STI) and asynchronous (ATI) time interleaving of AD converters. The STI front-end applies current mode integrating samplers whereas the ATI front-end applies mixers and filters. For the data link transmitter, an ultra-high-speed single-core SiGe BiCMOS DAC core will be shown. Moreover, we introduce the concept of D/A time interleaving with analog multiplexer circuits. Finally, we present a testbed for the test of a STI ADC front-end.

Abstract

A novel concept for digital-to-analog converters (DACs) has been introduced recently, to overcome their bandwidth limitations by combining the outputs of multiple DACs with an analog multiplexer (AMUX). In this paper, a behavioral model for a high-speed 2:1-AMUX is introduced, which significantly reduces the simulation time for a 2:1-AMUX-DAC system. The behavioral model is implemented in Matlab and fitted with simulation data from an electronic design automation tool for a high-speed 2:1-AMUX integrated circuit with a normalized mean square error \textless -20 dB. Eventually, multiple model parameters are varied in order to study their impact on the system's behavior.