PANNA: A 558 TOPS/W Pipelined All-Analog Neural Network Accelerator in 22 nm FD-SOI
Jakob Finkbeiner, Raphael Nägele, Manuel Wittlinger, Markus Grözing, Manfred Berroth, Georg Rademacher
Abstract — Analog computing offers intrinsic energy and latency benefits that makes it attractive for real-time and edge applications. Conventional analog accelerators suffer from repeated conversions between analog and digital domain, which degrades efficiency and throughput. We propose an all-analog pipelined neural network accelerator architecture in 22 nm FD-SOI CMOS. Measurements of a demonstrator ASIC with analog I/Os and 6 bit weights are presented. The system energy efficiency is 290 TOPS/W or 558 TOPS/W if the energy for bias generation is neglected. The pipelined architecture achieves a throughput of 500M inferences/s and a latency of 1 ns/layer.